The invention relates to a substrate voltage control circuit of a semiconductor memory. In a semiconductor memory, the voltage on a substrate having a region where a memory cell is formed is controlled. As a conventional semiconductor device, there is a circuit as disclosed in Japanese Patent Laid-Open Publication No. 62-121996. In this circuit, a substrate bias generation circuit generates a voltage to be applied to a substrate, and a voltage detection circuit detects whether the voltage to be applied to the substrate reaches a given voltage value.
In a conventional semiconductor memory, a voltage to be applied to a substrate has a predetermined value. If a threshold value of a transistor is shifted owing to variations in a fabricating process, or the like, there has occurred a case where data is inferiorly written on a memory cell or written data has not been stored.